Constraint Posting for Verifying VLSI Circuits
Proceedings of the Eleventh International Joint Conference on Artificial Intelligence. Planning, Scheduling, Reasoning About Actions. Pages 881-885.
Abstract
We appl y constraint posting to the problem of reasoning about function from structure . Constraint posting is a technique used by some planners to coordinate decisions . At each decision point constraints are posted that later decisions must obey . We use constraint posting to help verify that a circuit modelled at the analog level will exhibit its intended digital behavior. A circuit 's analog behavior depends not only on the circuit 's structure , but also on how the circuit is used. We post constraints to ensure that a circuit will only be used commensurate with its intended function. This research shows that while there is no ''function from structure ," there is function from structure and constraint posting . We have implemented these ideas in program that rapidly verifies large circuits.
@inproceedings{ijcai1989p141,
title = {Constraint Posting for Verifying VLSI Circuits},
author = {Weise, Daniel},
booktitle = {Proceedings of the Eleventh International Joint Conference on
Artificial Intelligence, {IJCAI-89}},
publisher = {International Joint Conferences on Artificial Intelligence},
editor = {N. S. Sridharan},
pages = {881--885},
year = {1989},
month = {8},
note = {Planning, Scheduling, Reasoning About Actions},
url = {https://ijcai.org/proceedings/1989/141},
}
TY - CPAPER TI - Constraint Posting for Verifying VLSI Circuits AU - Weise, Daniel T2 - Proceedings of the Eleventh International Joint Conference on Artificial Intelligence, IJCAI-89 PB - International Joint Conferences on Artificial Intelligence PY - 1989 SP - 881 EP - 885 UR - https://ijcai.org/proceedings/1989/141 ER -Copied
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