---
title: "Constraint Posting for Verifying VLSI Circuits"
authors:
  - "Daniel Weise"
doi: ""
url: "https://ijcai.org/proceedings/1989/141"
pdf: "https://ijcai.org/proceedings/1989/0141.pdf"
venue: "Proceedings of the Eleventh International Joint Conference on Artificial Intelligence"
year: 1989
pages: "881-885"
track: "Planning, Scheduling, Reasoning About Actions"
keywords:
---

# Constraint Posting for Verifying VLSI Circuits

Daniel Weise

*Proceedings of the Eleventh International Joint Conference on Artificial Intelligence*, pages 881-885.

## Abstract

We appl y constraint posting to the problem of reasoning about function from structure . Constraint posting is a technique used by some planners to coordinate decisions . At each decision point constraints are posted that later decisions must obey . We use constraint posting to help verify that a circuit modelled at the analog level will exhibit its intended digital behavior. A circuit 's analog behavior depends not only on the circuit 's structure , but also on how the circuit is used. We post constraints to ensure that a circuit will only be used commensurate with its intended function. This research shows that while there is no ''function from structure ," there is function from structure and constraint posting . We have implemented these ideas in program that rapidly verifies large circuits.