ACCFormer: Predicting Analog Circuit Performance Metrics via Topology-Aware Transformers

1 Introduction

With the development of electronic design automation (EDA) [Reis, 2022] and advanced manufacturing technologies [Ji et al., 2019], efforts have been made to integrate AI into the design of analog integrated circuits (ICs) [Zadeh and Elamien, 2025]. This aims to shorten chip design cycles, enabling rapid product iteration to meet evolving market demands. In this work, we focus on the following task: predicting key performance metrics (e.g., DC gain, phase margin) of analog circuits manufactured at a specified process node (e.g., SMIC 65nm), based on circuit design parameters (e.g., device sizes, bias conditions) and interconnect relationships (netlists) between devices, as illustrated in Figure 1.

Automating this process is crucial for addressing a major bottleneck in contemporary analog design: reusing intellectual properties (IPs) across process nodes 1 [Brunoli et al., 2002]. By avoiding "reinventing the wheel", chip design companies can reduce design costs and accelerate product iteration. Currently, migrating existing IPs to new process nodes requires extensive manual recalibration by specialized analog engineers to compensate for shifts in device characteristics due to process variations, which consumes significant time and human resources. Compounding the issue, most existing EDA software relies on solving massive nonlinear equations based on underlying physical laws to calculate performance changes in analog circuits when altering process nodes and design parameters [Scheffer et al., 2018]. While accurate, a single simulation typically takes several hours for large scale analog ICs, hindering automated parameter searches and rapid design iterations. With the accumulation of data from simulation and production, coupled with advancements in AI, the industry has shifted toward data-driven approaches [Shin, 2023] rather than solving massive equation systems to achieve rapid prediction of metrics.

† Corresponding authors. Primary contact: Bin Li.

Previous work primarily employed simple machine learning methods [Huang et al., 2021] combined with feature engineering for performance prediction. While effective in limited scenarios, this approach suffers from significant shortcomings: artificially designed features inherently lack flexibility and are tightly coupled to specific circuit architectures. Analog circuit design exhibits diverse topological structures, and the mapping between design parameters and performance metrics is not only highly nonlinear but also fundamentally dependent on the specific interconnections between devices. For example, while the Telescopic Cascode Amplifier (Figure 1 (a)) and Folded Cascode Amplifier (Figure 1 (b)) share identical device quantities and types, their differing topologies enable the former to deliver higher voltage gain and the latter to provide greater output swing under matching device parameters [Razavi, 2005]. These manually designed features often fail to transfer to new circuit topologies, necessitating expertdriven feature redesign for new circuits.

Inspired by the small signal analysis [Razavi, 2021], we approach this problem from the perspective of graph regression. We model circuit as a graph, where devices serve as nodes and their design parameters as node attributes. The netlist is transformed into an adjacency list of the graph to characterize the connections between nodes. By identifying key subgraphs in the circuit, we address this problem from a data-driven perspective rather than manually designed feature engineering. Based on this, we propose ACCFormer, a novel topology-aware model for Analog CirCuit performance prediction based on the TransFormer architecture [Vaswani et al., 2017]. To leverage the device and topology information of circuits, we propose a Topology-Aware Attention layer. It converts the circuit netlist into connectivity masks, guiding the multi-head self-attention mechanism to focus on actually connected device pairs. To identify devices critical to circuit performance, we introduce a Performance-Oriented Filtering layer. Each performance metric to be predicted is encoded as a query vector. Through a cross-attention mechanism, a subset of key devices that most significantly impact specific performance metrics is dynamically selected from all device representations. Experiments on commercial process nodes demonstrate the accuracy and robustness of our proposed model, highlighting its potential to accelerate design cycles. Our contributions can be summarized as follows:

1 IPs refer to reusable, modular circuit designs. Process nodes denote the fabrication technology provided by a specific manufacturer. These concepts will be elaborated upon in Section 2.1.

• A Novel Perspective. We adopt a data-driven approach rather than physical simulation, addressing the performance metric prediction problem of analog circuits from the perspective of graph machine learning. By replacing the solution of complex equation systems with an end-toend black-box model, this paradigm can significantly improve computational speed while ensuring accuracy.
• ACCFormer. We propose ACCFormer, a novel Transformer framework for analog circuit performance prediction. By incorporating the Topology-Aware Attention and Performance-Oriented Filtering layers, our model captures both topological influences and identifies the devices that dominate specific circuit performances. Its hierarchical pipeline explicitly encodes circuit connectivity, overcoming the limitations of previous approaches to enable accurate prediction and device-level interpretability.
• Empirical Evidence. We conduct extensive experiments to evaluate the effectiveness of ACCFormer. Empirical evaluation demonstrates that our model achieves SOTA accuracy in cross-process migration. To the best of our knowledge, this is the first work to present a large-scale experimental validation on commercial process nodes for the performance metrics prediction task.

2 Preliminary

2.1 Basic Concepts

In IC design, a circuit Intellectual Property (IP) refers to a reusable, modular design block that implements a specific function (e.g., an amplifier, a data converter). Migrating a proven IP to a new manufacturing technology is essential for design reuse. A process node (e.g., SMIC 65nm) refers to a specific semiconductor fabrication technology, characterized by its physical design rules, manufacturer, and transistor properties. Different nodes exhibit distinct device behaviors, making a design that works perfectly in one node likely non-functional in another without adjustment. Thus, process migration is a fundamental yet costly challenge in IC design.

2.2 ProblemDefinition

We formalize the core task as Performance Metric Prediction (PMP) for analog circuits. Given a circuit's netlist (a graph description listing devices like transistors and their interconnections) and their associated design parameters (e.g., device sizes, bias conditions), the goal is to predict a vector of key analog performance metrics (e.g., gain, bandwidth, power). The mapping f : (G, P) → Y is highly nonlinear and topology-dependent, where G is the circuit graph describing the connection between devices, P is the set of device parameters, and Y is the performance vector. The task extends to a cross-process PMP scenario, where a model trained on data from a source process node must be adapted to accurately predict performance for the same circuit topology in a target process node, given only very limited data from the target.

3 Methodology

3.1 Motivation

Previous research treats circuits as a flat collection of de-

vices and directly mapping all design parameters to perfor-

mance metrics, discarding the connectivity between compo-

nents. This unstructured approach suffers from two funda-

mental limitations that fail to align with the intrinsic charac-

teristics of analog circuits:

· Inadequate modeling of operating state dependence.

Transistor performance is highly dependent on its bias-

determined operating region. The same set of design pa-

rameters can drive a transistor into entirely different operat-

ing regions under varying conditions or peripheral circuitry,

leading to sharply distinct physical behaviour.

· Ignoring circuit topology. In analog design, performance

metrics emerge from the flow of signals and the interactions

among devices within a specific topology. Ignoring topol-

ogy equates to overlooking the physical essence of circuit

functionality, making it difficult for the model to establish

accurate correlations between performance indicators and

underlying device parameters.

In modern analog ICs, MOSFETs are a crucial component,

introducing the most nonlinearity into circuits. Under dif-

ferent bias conditions (part of the design parameters), MOS-

FETs fall into different operating regions, exhibiting vastly

different characteristics. As illustrated in Figure 2, in the

cutoff, ohmic, and saturation regions, the electrical behav-

ior of a MOSFET can be approximated by an ideal switch,

a variable resistor, and a voltage-controlled current source,

respectively. Since bias voltages are typically much larger

than input signals, we can locally linearize their behavior within a specific operating region using simple circuit elements. In classical circuit analysis, analog engineers first (1) determine the operating region of each MOSFET to (2) define its behavior, then (3) identify key signal paths and components through simplified circuits to (4) calculate final performance metrics. This 4-step progressive analytical approach, termed "small-signal analysis" [Razavi, 2021; Neamen, 2007], as shown in Figure 3, inspired our design.

3.2 Overall Architecture

We propose ACCFormer, a hierarchical reasoning framework that follows the principle of "from device characteristics, to topological interactions, and finally to performance correlations" [Razavi, 2021]. ACCFormer decomposes performance prediction into four stages based on small-signal analysis:

• Process-Parameter Fusion Embedding. By integrating design parameters with process knowledge, we generate an initial embedded tensor for each device to characterize its behavioral characteristics and performance potential at a specific process node, corresponding to the Step (1).
• Topology-Aware Attention. We utilize the connectivity masks extracted from netlists to guide the self-attention mechanism, strictly limiting information exchange to physically interconnected devices. This enables learning dependencies determined by circuit architecture. This module corresponds to the Step (2).
• Performance-Oriented Filtering. We introduce a set of learnable performance query vectors. Through a crossattention mechanisms, each query automatically focuses on the most critical subset of devices affecting its performance metrics. This module mimics the Step (3).
• Multi-Dimensional Prediction Head. In the model's output, filtered performance-related contextual information is mapped to specific performance metric predictions. This module aligns with the Step (4).

Our proposed model not only systematically addresses the shortcomings of previous flat models but also makes the decision-making process more interpretable, as it mimics the modular analytical logic of a design engineer.

3.3 Process-Parameter Fusion Embedding

This module aims to generate a comprehensive embedding for each device by fusing information from three aspects: its design parameters, the inherent characteristics of the process node, and its functional role within the circuit. The module receives the circuit netlist and device design parameters as its two primary inputs. The circuit netlist is used to define the device types and their interconnections, while the design parameters mainly include the width (W) and length (L) of each transistor, as well as the values of passive components such as resistors and capacitors. From these, the module constructs a unified representation through the following steps:

• Process-Characteristic Encoding. We construct a feature embedding Ti that encapsulates its inherent properties under the target process node, which includes fundamental physical parameters, parasitic characteristics, and device-type attributes (e.g. transistors, capacitors). We use T ∈ RD×dT to represent the matrix of these processcharacteristic embeddings for all D device types and dT represents the dimension of process embedding.
• Functional-block Annotation. We extracted the subfunctional blocks formed by each device and its adjacent devices (e.g., differential pair, current mirror). Each block type is associated with a learnable embedding, yielding a functional vector Fi for device i. These embeddings forms the matrix F ∈ RM×dF , where M represents the total number of all sub-functional blocks in the circuit and dF represents the dimension of function embedding.
• Design-Parameter Preprocessing. We apply a feature engineering that transforms the design parameters of transistors into compact indicators to measure its performance potential (e.g., drive capability). We denote the parameter matrix as P ∈ RN×dP , where N represents the device number in the circuit and dP represents the feature dimension.

For the ith device, its preliminary representation is composed of the three types of tensors mentioned above. While Ti and Pi are unique to the device, Fi must accommodate the case where a single device belongs to multiple sub-functional blocks. Therefore, its functional embedding Fi is defined as the the sum of the learnable embeddings of all sub-functional blocks assigned to it, which can be written as:

where F(i) represents the set of block types assigned to device i and ek represents the embedding vector of subfunctional block k. Finally the three tensors are concatenated to form the device's preliminary representation:

The composite matrix D = [DT1 , ..., DTn ]T will be processed through a shared MLP to obtain the final device embedding:

where d is the hidden dimension of MLP. Each row of H(0) represents the characterization embedding of a device.

3.4 Topology-Aware Attention

After completing the fusion of device information, we need to analyze the electrical characteristics exhibited by each device based on the circuit topology. To this end, we introduce the Topology-Aware Attention module. By stacking multiple-head self-attention layers (Multi-Head SelfAttention, MHSA) and incorporating attention masks derived from the netlist, this module restricts correlation coefficients to exist only between topologically connected devices.

The circuit netlist is quantified as a connection mask matrix CM ∈ {0,-∞}N×N , which is used to explicitly constrain the attention range and prevent the devices from focusing on unconnected devices, thereby avoiding the influence of noise: only when there is a direct or indirect signal path (i.e., an electrical connection) between devices i and j, CMij = 0, can information be exchanged between them. Otherwise CMij = -∞, it will completely block the attention between unrelated devices. A crucial design consideration is that although Vdd (the power supply) and GND (ground) are topologically connected to many devices, they belong to the global reference potential nodes and do not constitute specific signal transmission paths. Consequently, if device i and device j are connected only through VDD or GND, we define that there is no functional connection between device i and device j, so we set CMij = -∞.

Within this module, H(0) serves as the input sequence from which the Query (Q), Key (K), and Value (V ) are linearly projected. The connectivity attention mask CM is directly incorporated into the attention computation to restrict information exchange to topologically connected devices. For the I-th attention block(where l = 1, 2, ......,L) the output of the block as follows:

where H(l-1) ∈ RN×d represents the output of the previous block(H(0) is the output of Process-Characteristic Encoding module), W Q,(l) h ,W K,(l) h ,W V,(l) h ∈ Rd×dk and W O,(l) ∈ Rh·dk×d are projection matrices for the l-th block, dk is the feature dimension per head, h is the number of attention heads, and the attention mask CM is shared across all blocks.

3.5 Performance-Oriented Filtering

We introduce a set of learnable performance embeddings Qperf ∈ RM×d , where M represents the number of performance metrics to be predicted. Each parameter metric embedding qm is designed to implicitly encapsulate the types of analysis (e.g., DC bias or AC sensitivity) that its corresponding performance metric relies on.

We take the performance embeddings Qperf ∈ RM×d and the device tensors H(L) from the previous module incorporating global structural information as both Keys and Values, which are then fed into a Multi-Head Cross-Attention layer. This process enables each performance encoding to attend to all devices and highlight those that exert the most significant impact on it through attention weights. The calculation for cross-attention can be referenced from the steps listed in the previous subsection, and we will not elaborate further here.

The output of the cross-attention layer C is then refined through a feed-forward network (FFN) followed by layer normalization (LayerNorm). The computation is as follows:

The final embedding C′ ∈ RM×d contains the final contextual representations for each performance metric after the crucial device screening and feature refinement, and serves as the direct input to the multi-dimensional prediction head.

3.6 Multi-Dimensional Prediction Head

We now have an embedding C′ that encapsulates the key information, and to map it back to the corresponding performance metrics, we can decode it using some simple decoders. We employ a shared MLP to serve as the decoder. It integrates the critical device information contained within each performance metric representation to generate the final prediction results ˆ y, where ˆy ∈ RM for all M target metrics.

3.7 Discussion: FromFirst Principle to Data

Traditional methods are based on first principles, where linear equations are formulated using Kirchhoff's voltage and current laws and then solved to obtain circuit responses. This white-box approach relies on complete knowledge of the circuit's structure and component parameters. While accurate, solving large systems of equations is time-consuming, especially as circuit sizes increase and various high-order effects of MOSFETs are considered, which makes the process even more cumbersome. In contrast, our approach encodes circuit components as embeddings and uses a decoder to predict performance metrics. This constitutes a black-box model. Through a data-driven method, we train the model to learn the mapping from circuit descriptions to performance metrics.

4 Experiments

4.1 Settings

Dataset Description. We constructed our dataset using circuit simulation data from two commercial process nodes: SMIC 180nm as the source node and SMIC 65nm as the target node. Simulations were performed in Cadence Virtuoso for two classic analog building blocks considered in this study: 5T-OTA and two-stage OP-AMP.

To ensure data diversity and mitigate the bias introduced by the highly nonlinear design space (where many random parameter sets lead to non-functional circuits), we adopted an active sampling strategy. For the source node, we initially performed 50,000 simulations per topology and then retained 10,000 balanced samples that adequately represent both functional and non-functional design regions. For the target node, we performed 5,000 simulations per topology and retained 1,000 balanced samples, reflecting the practical scenario of limited data availability in a new process.

Baselines for Comparison. We compare our ACCFormer with the following baselines:

• MLP: MLP was the model adopted in previous research on this problem [Wu and Savidis, 2022].
• MLPembedding: Since embeddings of device types and subfunctions are introduced in ACCFormer, we also incorporate these embedding into the input for fairness.
• ResMLP: ResMLP introduces a residual structure on the basis of the conventional MLP.
• ResMLPembedding: Consistent withMLPembedding, we also introduce the embedding into ResMLP to ensure the fairness of input comparison.

Implementation Details. Our model is implemented using PyTorch 2.5.1 and trained on an NVIDIA A800 GPU. We employ the AdamW optimizer with a batch size of 128. The initial learning rate is set to 1 × 10-4 for the 5T-OTA and 3 × 10-4 for the Two-Stage Op-Amp, and is halved every 20 epochs. The hidden dimension of all models is fixed at 512. For ACCFormer, the number of topology-aware attention and attention heads are selected as 3 and 8, correspondingly.

Evaluation Metrics. We leverage Loss and Coefficient of Determination(R2 ) for evaluation, where Loss is the average of the Mean Squared Error (MSE) and the Mean Absolute Error (MAE). A smaller value of Loss and a larger R2 indicate better performance of the model.

4.2 Model Comparison

According to the results in Table 1, our proposed ACCFormer demonstrates remarkable improvements over the baseline models across all datasets and metrics. While MLP and ResMLP achieve competitive results on simpler circuits like the 5T-OTA, MLP generalizes better for complex metrics such as CMRR, especially in structurally intricate designs like the two-stage op-amp, due to its lower overfitting tendency. Incorporating embeddings substantially boosts performance by encoding topological cues, but MLP-based models remain limited by their flat architecture. In contrast, ACCFormer excels at leveraging topological information, showing narrow margins in simple cases but significantly wider advantages in complex, highly nonlinear scenarios.

4.3 Ablation Study

Effects of Topology-Aware Attention. We construct an additional variant termed Topology-Aware Attention-Free, recorded as TAAF, in which this module is entirely removed while keeping other components unchanged. The results demonstrate that the standard model outperforms TAAF, which verifies that the Topology-Aware Attention module can effectively capture topological structural information.

Effects of Performance-Oriented Filtering. To evaluate the contribution of the Performance-Oriented Filtering module, we construct an additional variant termed PerformanceOriented Filtering-Free, recorded as POFF, in which this module is entirely removed while keeping all other components of ACCFormer unchanged. The results show that our proposed module can effectively identify and highlight the most influential devices for each target performance metric.

5T-OTA (SOURCE)

5T-OTA (TARGET)

Two-Stage OP-AMP (SOURCE)

Two-Stage OP-AMP (TARGET)

4.4 Hyperparameter Study

We investigate the effects of the number of Topology-Aware Attention blocks L, the number of heads Nh and the hidden layer dim C. The results are shown in Fig 4(a) illustrates that the model performance improves as L increases, reaches its best at L = 3, and then deteriorates when L = 4. Fig 4(b) shows that the model performance improves with the increase of Nh, but the improvement between Nh=8 and Nh = 16 is marginal. Fig 4(c) demonstrates the variation of model performance with the hidden layer dimension, where the best performance is achieved at C = 256.

4.5 Visualization Study

To further elucidate the internal behavior of ACCFormer, we visualize how the attention distribution in the PerformanceOriented Filtering (POF) module evolves as the model depth increases. Figure 5 presents the attention heatmaps for a given set of valid design parameters of the two-stage op-amp, comparing the POF module's outputs after L = 1 and L = 3 Topology-Aware Attention blocks. Given that metrics like UGF and Phase Margin involve complex pole-zero analyses, we focus our interpretation on Positive Slew Rate, DC Gain, and CMRR, whose first-order analytical expressions are:

where Iss is the bias current, Cc is the compensation capacitor, roi is the output resistance of transistor i and Rss is the output resistance of the tail current source. The heatmaps align remarkably well with these theoretical insights:

• Positive Slew Rate. For L = 1, the POF module disperses attention to several non-current-mirror transistors (X1-X8, except X2, since when testing the swing rate, the output is directly connected to the gate terminal of X2.) and pays little attention to Ibias For L = 3, it shifts focus primarily to the devices most relevant to the slew rate formula, demonstrating a more physics-aware concentration.
• DC Gain. The L = 1 model shows non-zero attention to the capacitor, whereas the L = 3 model correctly ignores it. This is consistent with circuit theory, as capacitor has negligible effect at the low frequencies relevant to the gain.
• CMRR. With L = 3, attention is almost exclusively placed on the tail current source transistor (X5), the key component in the CMRR expression. The channel length of the tail current source transistor directly determines the performance of the CMRR. In contrast, the L = 1 model also attributes some importance to X6, a transistor whose parameters do not directly influence CMRR.

This visualization study confirms that deeper TopologyAware Attention blocks enable ACCFormer to progressively refine its structural understanding, guiding the PerformanceOriented Filtering module to allocate attention in a manner that is both focused and consistent with circuit principles.

5 RelatedWorks

AI4EDA. The application of machine learning and artificial intelligence in electronic design automation (AI4EDA) [Yu, 2023; Shin, 2023; Huang et al., 2021] has evolved significantly, transitioning from computer-aided design (CAD) [Kahng and Koushanfar, 2015; Catanzaro et al., 2008] to AIassisted EDA [Wu et al., 2022], and more recently, toward AI-native and agentic design paradigms [Zang et al., 2025; Wu et al., 2024]. This evolution is driven by the increasing complexity of ICs and the need to manage vast design spaces beyond human capability. A prominent application of AI in EDA is design space exploration and optimization. Tools like Synopsys's DSO.ai [Verma, 2024; Venkatachar, 2021] leverage reinforcement learning to autonomously search for optimal PPA (Power, Performance, Area) solutions within the enormous solution space of chip design. Similarly, Cadence's Cerebrus [Metcalfe, 2021] employs generative AI to automate and optimize the IC design flow, achieving significant improvements in throughput. For verification, which consumes a substantial portion of the design cycle, AI-driven platforms such as the Verisium Platform [Nguyen et al., 2024] and Synopsys's VSO.ai [Lnu, ; Reddy, 2024] utilize machine learning to accelerate coverage convergence, automate root cause analysis.

Performance Metric Prediction. Early and impactful research includes Google's work on chip placement [Goldie and Mirhoseini, 2024] using graph neural networks (GNNs) [Mirhoseini et al., 2021; El Sayed et al., 2025] and reinforcement learning [Markov, 2023; Mirhoseini et al., 2020], which demonstrated that AI could produce superhuman results in optimizing physical design objectives. For analog and mixed-signal circuits, research has focused on overcoming the "black art" nature of design. Projects like BAG [Crossley et al., 2013; Hakhamaneshi et al., 2019] and more recent frameworks such as ALIGN [Kunal et al., 2019; Dhar et al., 2020], MAGICAL[Xu et al., 2019; Chen et al., 2020], and FALCON [Mehradfar et al., 2025] explore automated circuit sizing and layout generation . Commercial tools like Synopsys's ASO.ai [Synopsys Inc., 2026] apply reinforcement learning to accelerate simulation and characterization across PVT (Process, Voltage, Temperature) corners.

6 Conclusion and FutureWork

In this work, we addressed the critical challenge of predicting the performance metrics of analog circuits across different semiconductor process nodes. Moving beyond simulation-heavy physical solvers and inflexible featurebased approaches, we reformulated the problem from a graph machine learning perspective. To this end, we introduced ACCFormer, a topology-aware Transformer model for accurate and interpretable prediction of analog circuit performance across process nodes. By framing the problem as graph regression and integrating circuit connectivity into the attention mechanism, our method outperforms traditional approaches, enabling faster design cycles without costly simulations. In the future work, we will refine the graph representation to the port level for more granular circuit modeling.

Appendix

To facilitate understanding of the performance prediction task discussed in this paper, this appendix summarizes the main analog circuit performance metrics involved in our experiments. These metrics describe different aspects of circuit behavior, including low-frequency amplification, frequency response, closed-loop stability, common-mode noise rejection, and large-signal transient speed.

• DC Gain (Av). The DC gain measures the small-signal voltage amplification capability of an analog circuit at low frequency. It is usually defined as the ratio between the output voltage variation and the input voltage variation, i.e., Av = vout/vin. A higher DC gain generally indicates stronger amplification capability and better accuracy in feedback-based analog systems.
• Unity-Gain Frequency (UGF). The unity-gain frequency denotes the frequency at which the magnitude of the openloop voltage gain drops to one, or equivalently 0dB. It characterizes the effective bandwidth of an amplifier and reflects how fast the circuit can respond to input signal variations. A larger UGF usually indicates a wider operating bandwidth and faster settling in practice.
• Phase Margin (PM). The phase margin is a stability metric measured at the unity-gain frequency. It is defined as the difference between the circuit phase and -180◦ when the loop gain magnitude reaches unity. A sufficient phase margin indicates that the amplifier is less likely to oscillate and has better closed-loop stability and reduced ringing.
• Common-Mode Rejection Ratio (CMRR). The commonmode rejection ratio measures the ability of a differential circuit to suppress common-mode signals while amplifying differential-mode signals. It is commonly defined as the ratio between the differential-mode gain and the commonmode gain. A higher CMRR indicates stronger immunity to common-mode noise and mismatch-induced disturbances.
• Positive Slew Rate (SR). The positive slew rate describes the maximum rising rate of the output voltage under a large-signal transient response. It is typically expressed as SR+ = max(dvout/dt) during the rising transition. A higher positive slew rate indicates that the circuit can charge the load or compensation capacitor more rapidly, enabling faster large-signal response in practice.

Contribution Statement

Bowen Liao and Yutong Feng contributed equally to this work.

Acknowledgments

This work was partially supported by the Guangdong S&T Programme, China (2022B0101180001), as well as partially by the Engineering Research Center of Design and Technology Co-Optimization of Integrated Circuits, Ministry of Education, China.