The Graph’s Apprentice: Teaching an LLM Low-Level Knowledge for Circuit Quality Estimation

Moravej, Reza; Bodhe, Saurabh; Zhang, Zhanguang; Chételat, Didier; Tsaras, Dimitrios; Zhang, Yingxue; Zhen, Hui-Ling; Hao, Jianye; Yuan, Mingxuan

doi:10.24963/ijcai.2025/1033

The Graph’s Apprentice: Teaching an LLM Low-Level Knowledge for Circuit Quality Estimation

Reza Moravej, Saurabh Bodhe, Zhanguang Zhang, Didier Chételat, Dimitrios Tsaras, Yingxue Zhang, Hui-Ling Zhen, Jianye Hao, Mingxuan Yuan

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Proceedings of the Thirty-Fourth International Joint Conference on Artificial Intelligence. AI4Tech: AI Enabling Technologies. Pages 9296-9304.

https://doi.org/10.24963/ijcai.2025/1033

Keywords

Domain-specific AI4Tech: Other AI4Tech applications
AI4Tech infrastructure/systems: AI chips, AI sensors, AI computers
Advanced AI4Tech: Generative and LLMs-driven AI4Tech

Abstract

Logic synthesis is a crucial phase in the circuit design process, responsible for transforming hardware description language (HDL) designs into optimized netlists. However, traditional logic synthesis methods are computationally intensive, restricting their iterative use in refining chip designs. Recent advancements in large language models (LLMs), particularly those fine-tuned on programming languages, present a promising alternative. This work proposes augmenting LLMs with predictor networks trained to estimate circuit quality directly from HDL code. To enhance performance, the model is regularized using embeddings from graph neural networks (GNNs) trained on Look-Up Table (LUT) graphs, thereby incorporating lower-level circuit insights. The proposed method demonstrates superior performance compared to existing graph-based RTL-level estimation techniques on the established benchmark OpenABCD, while providing instant feedback on HDL code quality.

Reza Moravej, Saurabh Bodhe, Zhanguang Zhang, Didier Chételat, Dimitrios Tsaras, Yingxue Zhang, Hui-Ling Zhen, Jianye Hao, and Mingxuan Yuan. 2025. The Graph’s Apprentice: Teaching an LLM Low-Level Knowledge for Circuit Quality Estimation. In Proceedings of the Thirty-Fourth International Joint Conference on Artificial Intelligence, IJCAI-25. IJCAI, 9296–9304. https://doi.org/10.24963/ijcai.2025/1033

@inproceedings{ijcai2025p1033,
  title     = {The Graph’s Apprentice: Teaching an LLM Low-Level Knowledge for Circuit Quality Estimation},
  author    = {Moravej, Reza and Bodhe, Saurabh and Zhang, Zhanguang and Chételat, Didier and Tsaras, Dimitrios and Zhang, Yingxue and Zhen, Hui-Ling and Hao, Jianye and Yuan, Mingxuan},
  booktitle = {Proceedings of the Thirty-Fourth International Joint Conference on
               Artificial Intelligence, {IJCAI-25}},
  publisher = {International Joint Conferences on Artificial Intelligence Organization},
  editor    = {James Kwok},
  pages     = {9296--9304},
  year      = {2025},
  month     = {8},
  note      = {AI4Tech: AI Enabling Technologies},
  doi       = {10.24963/ijcai.2025/1033},
  url       = {https://doi.org/10.24963/ijcai.2025/1033},
}

TY  - CPAPER
TI  - The Graph’s Apprentice: Teaching an LLM Low-Level Knowledge for Circuit Quality Estimation
AU  - Moravej, Reza
AU  - Bodhe, Saurabh
AU  - Zhang, Zhanguang
AU  - Chételat, Didier
AU  - Tsaras, Dimitrios
AU  - Zhang, Yingxue
AU  - Zhen, Hui-Ling
AU  - Hao, Jianye
AU  - Yuan, Mingxuan
T2  - Proceedings of the Thirty-Fourth International Joint Conference on Artificial Intelligence, IJCAI-25
PB  - International Joint Conferences on Artificial Intelligence Organization
PY  - 2025
SP  - 9296
EP  - 9304
DO  - 10.24963/ijcai.2025/1033
UR  - https://doi.org/10.24963/ijcai.2025/1033
ER  -