{"type":"ScholarlyArticle","title":"Automated CPU Design by Learning from Input-Output Examples","authors":[{"name":"Shuyao Cheng","slug":"shuyao-cheng","given":"Shuyao","family":"Cheng","affiliation":"State Key Lab of Processors , Institute of Computing Technology , Chinese Academy of Sciences; University of Chinese Academy of Sciences; Cambricon Technologies"},{"name":"Pengwei Jin","slug":"pengwei-jin","given":"Pengwei","family":"Jin","affiliation":"State Key Lab of Processors , Institute of Computing Technology , Chinese Academy of Sciences; University of Chinese Academy of Sciences; Cambricon Technologies"},{"name":"Qi Guo","slug":"qi-guo","given":"Qi","family":"Guo","affiliation":"State Key Lab of Processors , Institute of Computing Technology , Chinese Academy of Sciences"},{"name":"Zidong Du","slug":"zidong-du","given":"Zidong","family":"Du","affiliation":"State Key Lab of Processors , Institute of Computing Technology , Chinese Academy of Sciences; Shanghai Innovation Center for Processor Technologies"},{"name":"Rui Zhang","slug":"rui-zhang","given":"Rui","family":"Zhang","affiliation":"State Key Lab of Processors , Institute of Computing Technology , Chinese Academy of Sciences"},{"name":"Xing Hu","slug":"xing-hu","given":"Xing","family":"Hu","affiliation":"State Key Lab of Processors , Institute of Computing Technology , Chinese Academy of Sciences; Shanghai Innovation Center for Processor Technologies"},{"name":"Yongwei Zhao","slug":"yongwei-zhao","given":"Yongwei","family":"Zhao","affiliation":"State Key Lab of Processors , Institute of Computing Technology , Chinese Academy of Sciences"},{"name":"Yifan Hao","slug":"yifan-hao","given":"Yifan","family":"Hao","affiliation":"State Key Lab of Processors , Institute of Computing Technology , Chinese Academy of Sciences"},{"name":"Xiangtao Guan","slug":"xiangtao-guan","given":"Xiangtao","family":"Guan","affiliation":"University of Science and Technology of China"},{"name":"Husheng Han","slug":"husheng-han","given":"Husheng","family":"Han","affiliation":"State Key Lab of Processors , Institute of Computing Technology , Chinese Academy of Sciences; University of Chinese Academy of Sciences"},{"name":"Zhengyue Zhao","slug":"zhengyue-zhao","given":"Zhengyue","family":"Zhao","affiliation":"State Key Lab of Processors , Institute of Computing Technology , Chinese Academy of Sciences; University of Chinese Academy of Sciences"},{"name":"Ximing Liu","slug":"ximing-liu","given":"Ximing","family":"Liu","affiliation":"State Key Lab of Processors , Institute of Computing Technology , Chinese Academy of Sciences; University of Chinese Academy of Sciences"},{"name":"Xishan Zhang","slug":"xishan-zhang","given":"Xishan","family":"Zhang","affiliation":"State Key Lab of Processors , Institute of Computing Technology , Chinese Academy of Sciences; Cambricon Technologies"},{"name":"Yuejie Chu","slug":"yuejie-chu","given":"Yuejie","family":"Chu","affiliation":"State Key Lab of Processors , Institute of Computing Technology , Chinese Academy of Sciences"},{"name":"Weilong Mao","slug":"weilong-mao","given":"Weilong","family":"Mao","affiliation":"State Key Lab of Processors , Institute of Computing Technology , Chinese Academy of Sciences"},{"name":"Tianshi Chen","slug":"tianshi-chen","given":"Tianshi","family":"Chen","affiliation":"Cambricon Technologies"},{"name":"Yunji Chen","slug":"yunji-chen","given":"Yunji","family":"Chen","affiliation":"State Key Lab of Processors , Institute of Computing Technology , Chinese Academy of Sciences; University of Chinese Academy of Sciences"}],"abstract":"Designing a central processing unit (CPU) requires intensive manual work of talented experts to implement the circuit logic from design specifications. Although considerable progress has been made in electronic design automation (EDA) to relieve human efforts, all existing EDA tools require hand-crafted formal program codes (e.g., Verilog, Chisel, or C) as the input. To automate the CPU design without human programming, we are motivated to learn the CPU design from only input-output (IO) examples. The key challenge is that the learned CPU design should have almost zero tolerance for inaccuracy, which makes well-known approximate algorithms such as neural networks ineffective.\r\n\r\nWe propose a new AI approach to generate the CPU design in the form of a large-scale Boolean function, from only external IO examples instead of formal program code. This approach employs a novel graph structure called Binary Speculative Diagram (BSD) to approximate the CPU-scale Boolean function accurately. We propose an efficient BSD expansion method based on Boolean Distance, a new metric to quantitatively measure the structural similarity between Boolean functions, gradually increasing the design accuracy up to 100%. Our approach generates an industrial-scale RISC-V CPU design within 5 hours, reducing the design cycle by about 1000x without human involvement. The taped-out chip, Enlightenment-1, the world's first CPU designed by AI, successfully runs the Linux operating system and performs comparably against the human-design Intel 80486SX CPU. Our approach even autonomously discovers human knowledge of the von Neumann architecture.","doi":"10.24963/ijcai.2024/425","url":"https://ijcai.org/proceedings/2024/425","pdf":"https://ijcai.org/proceedings/2024/0425.pdf","markdown":"https://ijcai.org/proceedings/2024/425.md","bibtex":"https://ijcai.org/proceedings/2024/bibtex/425","volume":{"slug":"2024","title":"Proceedings of the Thirty-Third International Joint Conference on Artificial Intelligence","short_title":"IJCAI 2024","url":"https://ijcai.org/proceedings/2024/","year":2024,"location":"Jeju, Korea","dates":"3-9 August 2024","editors":"Kate Larson","isbn":"978-1-956792-04-1","publisher":"International Joint Conferences on Artificial Intelligence Organization","doi_prefix":"10.24963/ijcai.2024"},"section":"Machine Learning","track":"Main Track","number":425,"pages":{"first":3843,"last":3853},"keywords":["Machine Learning: ML: Applications"],"videos":[],"references":[{"position":1,"raw":"[Adir et al., 2004] Allon Adir, Eli Almog, Laurent Fournier, Eitan Marcus, Michal Rimon, Michael Vinov, and Avi Ziv. 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