IMAGE PROCESSIKG BY EIPERIKENTAL ARRAYED PROCESSOR

1. IBTHODUCTION

Maay proposals for patter~ processing ha'f:e been aade to dat.e, and soae ha'f:e been practicallY ~lamented~ espec1ally !or certain industrial and 1118dical applications, in which special processors such as image ana!y:z.ers are in practical use . RoweT-er, aost iaage processors ~

only deal with binary images.tll

On the otherhaad, recently large-scale pattern processors ha"t:e been studies in soae research laboratories.(2J BoweTer there are stil1 probleas in dev.elopine image processors !or multi-le"t:eled images. ·or example, processors tend to become

too big and expensive ..

Howeverr r ecent developments in

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This work was contracted with the Agency of Industrial Science and Technology, Ministry of International ft'ade and ID.du.atl7, as a part of the ftational Research and Developaent Program "Pattern Information Processing Systea~

co11111ercially a'Dilable IC 1 s have had a protound etfect on the size~ speed~ and cost of hardware. In addition~ the aeed !or general purpose image processors is getting stronger. Thus~ the image processor presented here was axperiaental­ ly developed. The outstanding feature in our iaage processor IP is parallel processing ability ..

~his paper described the principles and ~sic operation in this IP.

2. DESIGI PLIRCIPLES

The aain points considered in establiah­

ing our IP are diacuased below.

Infor.ation ~uded ~ iaages depe~e on. the tw-cliaen.aioDal. arrangeaeat ot pixel's ..U.uas.. So two-c!Uien.siollal. ·emory access ia e~loyed tor data utilization. Thereforer the ·eaor.r waa separated into two distinct parte, one for images. and the other for control data. The foraer has useful tunetiona tor

parallel processing of images.

In image processinc; , the same operations are repeated many times. In these cases, increasing proces :_;ing speed by ordinary computer architectures is not efficient. Therefore, the execution unit in our IP was separated iato a conTentional aini­ coaputer's central processing unit and a parallel processing part. The fQraer aa1nly deals with control data and eoaetiaes processes pixels one by one, while the latter usually processes pixels by the parallel processing.

In the parallel processing part, an arrayed structure was adopted, mainly to increase processing speed. In pre­ processing of feature-extraction of images the same operator is executed at every sampling point.. !''or such position­ invariant processes. an arrayed structure is very useful. Many sampling data are inputted to many processing elements at a time. Then all processing elements execute the same operation simultanious!y. Increasing the mumber of processing elements by a certain factor should cause the processing time to decrease by the same factor.

One cause reducing the effect of an arrayed structure is the occurrance of irregular flow such as conditional jump. In such cases, all processing elements can not be controlled by one sequence. Some PEs will have to be in a halt state. 'l'o

avoid this problem and increase efficiency of parallel processing, a special micro­ processor was deTeloped which can absorb irregularities and do such special calculations as summing products, table look up and getting namming-distance at high speed.

lt is difficult to control the array. Therefore a usage of micro-instructions was planned to control executions in a processing element and data's !lows between the array and a picture memory.

3. SYSTEM OUTLINE

A block diagram of our IP is shown in F:lg. 1. It consists of .a parallel processing part and the other part. The former comprises a processing element array(PE Array), a picture memory(PM), local resisterslLR), a micro-instruction control(MC) and input/output controlliOC).

Image data are inputted through the IOC and stored in the PM. They are originally obtained 6 bits in the IOC. The image data are then transaitted to the PE Array through the LR. The LR can store a 4 x 4 local-image or an 8 x 8 one. The PE Array processes it parallelly, and the results are stored again in the PM.

The PM is a memory for images consisting of three banks of 256 x 256 pixels. The access to the PM is controlled by micro­ instructions in a program~ The accessing unit is a 4 x 4 square with the upper­ left corner address (4n,4m), or one pixel. The letters n and · stand for integer from 0 to 63.

The PE Array consists of sixteen process­ ing element(PE). Each PE is a special micro-processor comprising a controller, which interprets commands and controls calculations in synchronization with an external clock. ~he commands comprise addition, subtraction, multiplication, summing products, logical operation, t able look up and so on. Each PE has a 256 words 16 bits scratch pad memory. The scratch pad memory can store a sequence of PE commands. Therefore each PE can execute its own program. The depth of calculations is twelve bits long. The execution time is o. 35 Jl.. S and the cycle time of the PM is 0. 7 p.S.

The LR has shift functions in an 8 x 8 l ocal image. The PE Array can obtain the free 4 x 4 square pixels from the PM by these functions. Also, PEs can comunicate each other through the LR.

4. BASIC OPERATIONS

In order to describe functions in the PE Array, several notational definitions are given as fol1ows;

• D(x,y); a value of pixel(x,y) in the original image.

R(x,y); a result ~ a certain operation in a PE of the PE Array.

F() ,G(); functions ex~cuted by a combination of PE's commands.

In t he PE Array sixteen PEs process local images in the LR simultaneously. 'rherefore sixt een results~Hx,y); l

The representative basic operations i n the PE Array are as follows.

This is used for thresholding, contras t stretching and so on. Ia a thresholding of a 256 x 256 image, it takes about 11.5

• ( a) Data conversion. H( x,y) =.f{D(x,y)) mS .

(b) Local operation. R( x , y ):F(1D(x,y)) For example, in a case of two-dimentional filt erings the results are as follows .

4 4 R(x+m,y+n)= ~ E f(i,j)xD(x+i+m,y+j+m) i=O j:O O~mS3; O~n~3 where f(i,j)s are weight coefficients.

In all PEs, twenty-five times' executions of the PE command "SUM OF PRODUCT" are ~one. lt takes 34.4 mS in a 256 x 256 ~~age. H~ this local operation, spacial d~ffer~nt~ation, noise elimination. template m~tching, and so on are available.

• lc) Sequential processing. ~(x,y)=FOD(x,y),Q(x-s,y-t)) Q(x,y )=G(D(x,y) ~(x-s,y-t)) WhereQ is PE's internal states specified by several flags and contents of the scratch pad memory. '!he point (x-s,y-t) shows a preceding processing point to point (x,y). Values of letter s and t depend on a scanning in the PM. This calculation is used for histogram's calculation, area counting and so on. For example, the processing speed of obtaining pixel value's distributions is 28 mS.
• (d) Manipulation between two images.
• R(x,y):F(D 1 (x,y),1> 2 (x,y))

where D 1 (x,y) and IDi(x,y) show values of diff~rent images pixels. For example, it takes about 18 mS to get an add-image or exclusive OR-image from two images.

5. CONCLUSION

An image processor based on an arrayed structure was implemented. It deals with images consisting of 256 x 256 pixels and processes them by a 4 x 4 processing elements' array. It was constructed in 1977 and used to study processor's architecture for the object recognition. riy these studies, it has been established that the array of our IP is useful for high speed processing.

The basic operations i n the array are data conversions, local operations, sequential processings, manipulations between two images.and so on. By them, many kinds of image processing can be done in this array.